Senior roles at Rambus
3 new this week · 33 open · from company career pages
Official careers page: www.rambus.com/careers
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1–33 of 33, plus 2 newer ones with members for their first 5 days
| Role | Company | Location | Pay a year | Experience | Posted | Quick look |
|---|---|---|---|---|---|---|
| Principal Product EngineerLead / Manager | Rambus | San Jose, California Hybrid | $177k | 30+ yrs | ||
Principal Product Engineer at Rambus Product engineering
C++Linux | ||||||
| PE Logic DesignLead / Manager | Rambus | Bengaluru | – | 8+ yrs | ||
PE Logic Design at Rambus RTL design of PCIe IP blocks in SystemVerilog, including architecture, micro-architecture and FPGA prototyping
RecruitmentVerilogFPGA | ||||||
| PE Verification EngineeringLead / Manager | Rambus | Bengaluru Hybrid | – | 12+ yrs | ||
PE Verification Engineering at Rambus Pre-silicon RTL verification of DDR/HBM memory controller IP
PythonRecruitmentVerilog | ||||||
| PE Signal IntegrityLead / Manager | Rambus | Bengaluru Hybrid | – | 10+ yrs | ||
PE Signal Integrity at Rambus Signal integrity engineering
| ||||||
| Director FinanceDirector | Rambus | San Jose, California Hybrid | – | 10+ yrs | ||
Director Finance at Rambus Finance directing
AccountingLegal | ||||||
| SPE Signal IntegrityLead / Manager | Rambus | Johns Creek, Georgia Hybrid | – | 10+ yrs | ||
SPE Signal Integrity at Rambus Signal integrity engineering
| ||||||
| MTS Validation EngineeringLead / Manager | Rambus | San Jose, California Hybrid | – | 30+ yrs | ||
MTS Validation Engineering at Rambus Server system validation and bring-up of memory interface chips in a lab
PythonC++Compliance | ||||||
| PE Reliability EngineeringLead / Manager | Rambus | San Jose, California Hybrid | – | 30+ yrs | ||
PE Reliability Engineering at Rambus Principal reliability and new product introduction engineering for semiconductor chips
| ||||||
| Smts Verification EngineeringLead / Manager | Rambus | Hillsboro, Oregon Hybrid | – | 30+ yrs | ||
Smts Verification Engineering at Rambus Pre-silicon RTL design verification for DRAM controller IP
PythonVerilog | ||||||
| Sr Mgr Validation EngineeringLead / Manager | Rambus | San Jose, California Hybrid | – | 10+ yrs | ||
Sr Mgr Validation Engineering at Rambus Manage hardware validation and characterization of memory buffer chips
PythonProcurement | ||||||
| PE Validation EngineeringLead / Manager | Rambus | San Jose, California Hybrid | – | 30+ yrs | ||
PE Validation Engineering at Rambus Silicon lab validation and bring-up of memory interface chips
CompliancePython | ||||||
| Smts Analog EngineeringSenior | Rambus | Bengaluru | – | 5+ yrs | ||
Smts Analog Engineering at Rambus Analog/mixed-signal circuit design for memory interface chips
Verilog | ||||||
| Lead MTS Verification EngineeringLead / Manager | Rambus | Bengaluru Hybrid | – | 30+ yrs | ||
Lead MTS Verification Engineering at Rambus Chip verification engineering
PythonVerilog | ||||||
| Smts Layout DesignSenior | Rambus | Bengaluru Hybrid | – | 5+ yrs | ||
Smts Layout Design at Rambus Chip layout design for memory interface blocks
| ||||||
| Lead MTS Verification EngineeringLead / Manager | Rambus | Bengaluru Hybrid | – | 8+ yrs | ||
Lead MTS Verification Engineering at Rambus Chip verification engineering
PythonRecruitmentVerilog | ||||||
| Senior Power Platform developerSenior | Rambus | Bengaluru | – | 8+ yrs | ||
Senior Power Platform developer at Rambus Power Platform development
JavaScriptSQLAzureDevOpsPower BISalesforce | ||||||
| Principal Product EngineerLead / Manager | Rambus | San Jose, California Hybrid | – | 30+ yrs | ||
Principal Product Engineer at Rambus Semiconductor product engineer for new product introduction and ATE test of power management ICs
C++Linux | ||||||
| Director of Program ManagementDirector | Rambus | San Jose, California Hybrid | – | 10+ yrs | ||
Director of Program Management at Rambus Program management direction
ExcelPLCSOC | ||||||
| Lead Facilities AdministratorLead / Manager | Rambus | Bengaluru Hybrid | – | 6–8 yrs | ||
Lead Facilities Administrator at Rambus Facilities administration
ProcurementComplianceLegal | ||||||
| Lead MTS Pmic Application and Validation EngineerLead / Manager | Rambus | San Jose, California | – | 5+ yrs | ||
Lead MTS Pmic Application and Validation Engineer at Rambus PMIC application and validation engineering
PythonMarketingCompliance | ||||||
| PE Quality AssuranceSenior | Rambus | San Jose, California Hybrid | – | 5+ yrs | ||
PE Quality Assurance at Rambus Semiconductor supplier and customer quality engineering
AuditCompliance | ||||||
| SPE Analog EngineeringLead / Manager | Rambus | Johns Creek, Georgia Hybrid | – | 10+ yrs | ||
SPE Analog Engineering at Rambus Analog circuit engineering
Verilog | ||||||
| PE Logic DesignLead / Manager | Rambus | Hillsboro, Oregon Hybrid | – | 10+ yrs | ||
PE Logic Design at Rambus Logic design for electronic hardware
PythonVerilogFPGA | ||||||
| Director - Silicon IP SalesDirector | Rambus | San Jose, California Hybrid | – | 30+ yrs | ||
Director - Silicon IP Sales at Rambus Silicon IP sales director for interface and security products
Marketing | ||||||
| PE Logic DesignSenior | Rambus | Bengaluru | – | 8+ yrs | ||
PE Logic Design at Rambus Logic design for electronic hardware
RecruitmentVerilog | ||||||
| Principal PCIe Logic DesignLead / Manager | Rambus | Hillsboro, Oregon Hybrid | – | 8+ yrs | ||
Principal PCIe Logic Design at Rambus PCIe logic design
Verilog | ||||||
| PE Product EngineeringLead / Manager | Rambus | San Jose, California Hybrid | – | 30+ yrs | ||
PE Product Engineering at Rambus Semiconductor product engineering for new product introduction and test transfer
| ||||||
| MTS Logic DesignLead / Manager | Rambus | Hillsboro, Oregon Hybrid | – | 30+ yrs | ||
MTS Logic Design at Rambus Logic circuit design
VerilogCustomer support | ||||||
| Lead MTS Verification EngineeringLead / Manager | Rambus | Bengaluru Hybrid | – | – | ||
Lead MTS Verification Engineering at Rambus Chip verification engineering
PythonFPGACustomer support | ||||||
| Lead MTS Physical DesignLead / Manager | Rambus | Bengaluru | – | 10+ yrs | ||
Lead MTS Physical Design at Rambus Chip physical design
| ||||||
| Lead MTS Verification EngineeringLead / Manager | Rambus | Bengaluru Hybrid | – | – | ||
Lead MTS Verification Engineering at Rambus Chip verification engineering
PythonFPGACustomer support | ||||||
| SPE Applications/Validation EngineeringLead / Manager | Rambus | San Jose, California Hybrid | – | 12+ yrs | ||
SPE Applications/Validation Engineering at Rambus Applications and validation engineering
PythonMarketing | ||||||
| Technical Director ValidationDirector | Rambus | Johns Creek, Georgia Hybrid | – | 20+ yrs | ||
Technical Director Validation at Rambus Hardware validation and lab bring-up of memory interface chips
PythonFPGACompliance | ||||||
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Questions
- Is Rambus hiring for senior roles?
- Yes: 33 senior roles at Rambus are open on Rambus’s own careers site today, 3 of them posted in the last 7 days. Recent openings: Principal Product Engineer; PE Logic Design; PE Verification Engineering; PE Signal Integrity.
- Where do I apply for Rambus senior jobs?
- On Rambus’s own careers site, https://www.rambus.com/careers/. Every job on this page links to its listing there.
- Which site alerts me to new senior roles at Rambus?
- OpeningsFirst emails new senior roles at Rambus the day employers post them on their own career pages, checking 108,296 career sites. Many never reach LinkedIn. Listings older than 5 days are free to browse here; 33 are open on this page now.
- How do I hear about new senior roles at Rambus first?
- Members get new matching jobs by email at 8 am and 6 pm, within hours of being posted, so they apply among the first. It costs $9 a month.
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