Staff Electromechanical Packaging Engineer
Navitas Semiconductor · navitassemi.com
TorranceLead / Manager30+ yrs
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The job in short
Electromechanical packaging engineering.
Details
- Found
- 6 d ago · posted 2026-10-30
- Location
- Torrance, CA, USA
- Pay (as listed)
- $135,000–$165,000 a year
Full description
Job Details: Job Location: Torrance, CA - Torrance, CA, Position Type: Full Time, Salary Range: $135000.00 - $165000.00Salary/year, Job Purpose:
Navitas Semiconductor (Nasdaq: NVTS) is a next-generation power semiconductor leader driving innovation in gallium nitride (GaN) and high-voltage silicon carbide (SiC) technologies. Our products enable faster, more efficient power delivery across AI data centers, high-performance computing, energy and grid infrastructure, and industrial electrification.
With more than 30 years of combined expertise in wide bandgap technologies, GaNFast™ power ICs integrate GaN power, drive, control, sensing, and protection, delivering faster power delivery, higher system density, and greater efficiency. GeneSiC™ high-voltage SiC devices leverage patented trench-assisted planar technology to provide industry-leading voltage capability, efficiency, and reliability for medium-voltage grid and infrastructure applications.
We are seeking a Staff Electromechanical Packaging Engineer to join our fast-growing, collaborative team. The ideal candidate is self-motivated, energetic, and able to thrive in a high-growth, innovative environment, contributing directly to technologies that are shaping the future of power electronics.
Key Responsibilities and Duties:
The Electromechanical Packaging Engineer will be working with a Lead Engineer and be responsible for:
Support chip scale packaging design and HDI organic substrate layout for integrated voltage regulator product line.
Collaborate with substrate layout, ASIC design, and manufacturing engineers.
Create mechanical drawings for substrate fabrication and packaged part assembly. Work with vendors for components, assembly, and test.
Work with OSAT (Out-Source Assembly and Test) suppliers in establishing process baseline from prototype to mass production
Knowledge, Skills, Abilities, and Other Characteristics (KSAO’s)
Understanding of how electrical design requirements impact substrate layout and interconnect selection
Proficient with 3D mechanical CAD software (Creo, NX, Catia, etc.), generating mechanical drawings, and GD&T
Ability to read and create electrical schematics
Familiarity with tape out processes for wafers and substrate
Basic understanding of Form, Fit, Function elements in design for manufacturability (DFM).
willingness to learn new concepts and techniques and concepts
Familiarity with PCB design tools (Altium, Cadence, Mentor, etc.) is a plus
Basic understanding of component level thermal analysis is a plus
Qualifications: Required Qualifications
Basic
Minimum BS in Mechanical or Electrical engineering, MS or higher-level degree preferred.
3+ years’ experience with microelectronics packaging, and/or PCB design
Preferred
Knowledge of foundry processes and chip scale assembly processes
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