Develop, debug, and maintain production flows and automation in Tcl and Python for Synopsys Formality and Cadence Conformal, including handling of complex design classes Partner with physical design, front-end/synthesis, and signoff teams and with EDA vendors (Synopsys, Cadence) to qualify new tool releases, resolve critical tool issues, and support design teams through tapeout closure Independently drive technical decisions for the equivalency domain, identify root causes of ambiguous tool behavior, and define clear paths to resolution; mentor and serve as a backup for other engineers in the team Deliver measurable improvements in flow quality, runtime, and reliability, including regression coverage, documentation, and support turnaround for design teams Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience. These requirements include, but are not limited to the following specialized security screenings: This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience. 5+ years of experience in silicon CAD, physical design (logic synthesis), or design verification flows using tools such as Synopsys Fusion Compiler/Design Compiler and/or Cadence Genus/Innovus 3+ years of hands-on experience with formal equivalency checking tools (Synopsys Formality and/or Cadence Conformal) in advanced process nodes Proficiency in scripting and automation using Tcl and Python for developing and debugging production CAD flows Experience with ECO flows, including functional-metal ECO and low-power (UPF-aware) equivalency verification Experience qualifying and deploying EDA tool releases and working with vendor application engineers to drive issue resolution; familiarity with both Synopsys and Cadence equivalency tools Effective communication and collaboration skills, with the ability to work effectively with distributed design and CAD teams and translate complex tradeoffs into clear next steps Experience supporting multiple concurrent tapeouts and familiarity with cloud-based EDA compute environments