We are a startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. We are backed by top-tier VC firms and notable angel investors. The company is led by experienced builders and operators who have founded companies, taken them to scale, and exited successfully. We work with a strong sense of unity and shared responsibility, and we expect trust, integrity, and respect in how we collaborate and make decisions. We hold ourselves accountable to one another and to the quality of the work we deliver. Headquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada. We aim to create an environment where people are treated fairly, supported in their growth, and are empowered to do meaningful work alongside others who take the craft seriously. What We Need: We are looking for a Principal Physical Design Engineer to serve as an early member of our physical design team. You will own some of the most challenging physical implementation problems in the design, drive critical blocks and top-level integration, and help establish the methodologies required to achieve performance, power, area, and schedule targets. This is a deeply hands-on role for an engineer who can independently take complex designs from floorplan through signoff, solve difficult timing and implementation problems, and provide technical leadership across the broader physical design team. Key Responsibilities: • Own physical implementation of complex blocks and subsystems from synthesized netlist through signoff. • Develop floorplans considering hierarchy, macros, interfaces, congestion, timing, power, and routability. • Develop and optimize power-grid implementations and support IR-drop and electromigration closure. • Drive placement, optimization, clock-tree synthesis, routing, extraction, timing closure, and ECO implementation. • Own difficult setup, hold, signal-integrity, congestion, and physical implementation problems. • Lead timing closure across block boundaries and support top-level timing convergence. • Perform and drive static timing analysis across multiple modes and corners. • Support signal-integrity analysis and timing impact from crosstalk, variation, and physical effects. • Drive physical signoff, including DRC, LVS, antenna, density, connectivity, and related physical verification requirements. • Perform or support power integrity analysis, including static and dynamic IR drop and electromigration. • Develop implementation strategies for high-performance and physically challenging portions of the design. • Partner with RTL and architecture teams to identify implementation problems early and recommend architectural or logical changes where appropriate. • Work closely with DFT, verification, package, SI/PI, and other engineering teams to resolve cross-functional design issues. • Develop and improve physical design flows, scripts, automation, metrics, and methodologies. • Evaluate implementation results and identify opportunities to improve PPA, runtime, convergence, and design quality. • Provide technical guidance and mentorship to other physical design engineers. • Participate in design reviews, methodology reviews, and tapeout readiness assessments. • Serve as a technical escalation point for complex physical design and signoff issues. Required Skills and Qualifications: • 10+ years of ASIC or SoC physical design experience with multiple successful tapeouts. • Expert-level understanding of floorplanning, placement, CTS, routing, optimization, timing closure, ECOs, and physical verification. • Strong expertise in static timing analysis and multi-mode, multi-corner timing closure. • Strong understanding of power delivery, IR drop, electromigration, and signal integrity. • Demonstrated ability to independently own complex blocks or major portions of a chip through signoff. • Strong understanding of clock design, timing constraints, variation, extraction, and advanced-node physical effects. • Experience with industry-standard Cadence and/or Synopsys physical implementation and signoff tools. • Strong scripting and automation skills using Tcl, Python, Perl, or similar languages. • Ability to debug complex design problems across RTL, timing, physical implementation, and signoff domains. • Strong communication skills and ability to provide technical leadership without requiring formal management authority. Desired Skills: • Experience with advanced process nodes. • Experience with large, high-frequency or highly interconnected semiconductor designs. • Experience with hierarchical design and top-level physical integration. • Experience developing physical design methodologies and automation. • Experience working closely with package, SI/PI, and power-delivery teams. • Experience with multi-die, chiplet, or advanced packaging architectures. • Familiarity with EDA tool evaluation, benchmarking, and optimization. • Experience in an early-stage semiconductor environment. Additional Requirements: • Ability to independently drive complex technical problems to closure. • Comfortable operating across both detailed implementation work and broader chip-level design considerations. • Ability to work effectively in a highly collaborative, fast-paced engineering organization. Compensation: Target base salary for this role is $180,000 – $260,000 per year, plus meaningful equity, benefits, and 401(k). Salary ranges are determined by role, level, experience, and location. We are an equal opportunity employer. We value a range of perspectives and experiences and make employment decisions based on merit and business needs. We do not discriminate on the basis of legally protected characteristics. Agency Note: We do not accept resumes from agencies or search firms. Please do not forward candidate profiles through our careers page, email, LinkedIn messages, or directly to company employees. Any resumes submitted will be deemed the property of the company, and no fees will be paid in the event the candidate is hired. #LI-EW1