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Senior FPGA & Communications Engineer

GalaxEye Space Solutions Private Limited · galaxeye.space
BanglorenorthSenior4+ yrs
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The job in short

FPGA communications engineering.

FPGA

Details

Found
30 d ago · posted 2026-10-04
Location
Banglorenorth

Full description

At GalaxEye Space, we are pioneering the next generation of Earth observation solutions with our cutting-edge satellite technology. As a fast-growing space-tech startup, our mission is to revolutionize the way we gather, process, and deliver geospatial intelligence. Join us to become a part of an agile, high-impact team working at the forefront of space innovation. Senior FPGA & Communications Engineer | 4+ Years Experience We are seeking an innovative and driven Senior FPGA & Communications Engineer with a strong foundation in in developing HDL on FPGA . In this role, you will bridge the gap between hardware and software, architecting, designing, and optimizing advanced communication waveforms, transceiver architectures, and DSP algorithms for cutting-edge wireless applications. Key Responsibilities Knowing how to write precise Timing closure constraints Clock Domain Crossing (CDC): Mastery of safely moving data between asynchronous domains (ADC, DAC, DSP, and host bus) using asynchronous FIFOs and Gray coding to prevent metastability. Fixed-Point Arithmetic & Bit Growth: Knowing how to trace bit-width expansion across mixers and filters, applying proper rounding and saturation to prevent overflows without degrading the signal-to-noise ratio. Multi-Rate Filter Design: Expertise in designing and cascading Cascaded Integrator-Comb (CIC) and Finite Impulse Response (FIR) filters, including passband droop compensation. Hardened IP Integration: Experience instantiating and interfacing with the hardened PCIe Gen3 x4 or SERDES interfaces for high-throughput data streaming. Good to have Ability to structure HDL to infer FPGA pre-adders, and map NCO tables to EBRs while saving LRAMs for deep packet buffering. Digital Communication & RF Principles: Understanding the impact of NCO phase truncation spurs, I/Q amplitude/phase imbalances, DC offsets, and digital aliasing on analog RF performance. Requirements Qualification • Bachelor’s or Master’s degree in Electronics & Communication, Electrical Engineering, or a related scientific or engineering discipline. • 4+ Years experience with solid record of having developed HDL. Benefits What We Offer • Fair Compensation in line with current market standards. • Start-up Culture: Be part of a high-growth, innovation-driven team. • Flexible Working Hours to support work-life balance. • Open Culture: Freedom to explore, propose, and implement new ideas and processes. • Leadership Exposure: Opportunity to work directly with the Founding Team at GalaxEye. • Industry Mentorship: Work with advisors and mentors holding senior positions and decades of industry experience.

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