Company Overview: MosChip is a semiconductor and embedded system design company with a focus on Embedded, Turnkey ASICs, Mixed Signal IP, Semiconductor & Product Engineering and IoT solutions catering to Aerospace & Defense, Consumer Electronics, Automotive, Medical and Networking & Telecommunications. About the Role MosChip is seeking a experienced Senior IC Packaging Engineer to provide technical leadership in the coordination for architecture, design, and development of advanced IC Packaging, Multi-Chip Module (MCM), and System-in-Package (SiP) solutions. This role is ideal for a hands-on packaging expert with deep domain knowledge in advanced semiconductor packaging technologies, chiplet integration, high-speed interfaces, and heterogeneous system design. The successful candidate will drive package architecture and technology strategy across next-generation packaging platforms including FCBGA, 2.5D/RDL Fan-Out, Silicon Interposers, Chiplet-Based Architectures, and Heterogeneous Integration. The role requires close collaboration with design teams, foundries, OSATs, substrate vendors, and customers from feasibility assessment through volume production. Key Responsibilities • • Lead the architecture definition, and execution of advanced IC, MCM, and SiP packaging solutions for high-performance and high-density semiconductor products, based on cross functional coordination. • Own package technology selection, roadmap development, and architecture decisions to meet performance, power, cost, schedule, and scalability objectives. • Drive advanced packaging initiatives involving FCBGA, 2.5D packaging, RDL Fan-Out, Silicon Interposers, Embedded Die, and UCIe-based Chiplet Architectures. • Perform and guide package design, floor planning, and physical layout for high-speed interfaces including PCIe, CXL, UCIe, LPDDR5X, HBM, Ethernet, and multi-gigabit SerDes. • Define substrate stack-ups, bumping strategies, RDL architectures, power delivery networks, high-speed routing methodologies, and signal integrity best practices. • Lead package-level electrical, thermal, mechanical, and reliability analysis to achieve robust product performance and manufacturability. • Develop and implement Design-for-Manufacturing (DFM), Design-for-Test (DFT), Design-for-Reliability (DFR), and yield optimization strategies. • Collaborate with foundries, OSATs, substrate suppliers, assembly partners, and EDA vendors to drive technology qualification and manufacturing readiness. • Conduct package feasibility studies, technology evaluations, risk assessments, and cost-performance trade-off analyses. • Establish scalable packaging methodologies, design guidelines, and reusable flows across multiple projects and product families. • Mentor junior engineers and contribute to the growth of packaging capabilities within the organization. • Provide technical leadership in customer discussions, proposals, and pre-sales engagements related to advanced packaging solutions. Required Qualifications • • B.E./M.Tech in Electrical Engineering, Electronics Engineering, Semiconductor Technology, or related field. • 8-10+ years of industry experience in semiconductor package design and development for SoCs, ASICs, FPGA, AI/ML, Networking, HPC, Storage, or Memory products. • Strong hands-on expertise in: • Flip-Chip BGA (FCBGA); System-in-Package (SiP); Multi-Chip Modules (MCM) • Advanced substrates; RDL and Fan-Out Packaging; Silicon Interposers, • CSP, WLCSP, QFN, LQFP • Chiplet-based architectures and UCIe ecosystems • Deep understanding of SI, PI, TI & Mechanical Analysis related DFM concepts to achieve reliable and high yield packages • Proven experience in substrate design, escape routing, power distribution, high-speed package design, and package validation. • Hands-on experience with Cadence Allegro Package Designer (APD) or equivalent advanced package design tools. • Ability to work independently and drive complex programs from concept through production in a fast-paced environment. Preferred Qualifications • • Experience with HFSS, SIwave, Ansys Designer, Clarity, Icepak, CST, or equivalent simulation tools. • Knowledge of advanced interfaces such as UCIe, PCIe Gen5/Gen6, CXL, DDR5/LPDDR5, HBM, Ethernet, and AI accelerator packaging. • Experience working directly with leading foundries, OSATs, substrate manufacturers, and assembly/test partners. • Familiarity with advanced packaging roadmaps including 3D IC, Hybrid Bonding, CoWoS, Foveros, InFO, and next-generation heterogeneous integration technologies shall be a plus. • Scripting and automation skills using Python, Perl, TCL, or Shell scripting. • Experience supporting customer engagements, solution architecture reviews, and technical pre-sales activities. Education Requirements: B.E./M. Tech in Electrical, Electronics, Semiconductor Engineering, or related discipline Experience: 8 to 10 Years Domain: Advanced Semiconductor Packaging, SiP, MCM, Chiplets, FCBGA, 2.5D/3D Packaging, Heterogeneous Integration Location: Hyderabad Shift: General Work Week: Monday to Friday Quick Links: Who we are? : https://www.youtube.com/watch?v=4nvbzE-eUGk How we train? : https://www.youtube.com/watch?v=Yy5GtKP7ozk Contact: : www.moschip.com