The job in short
Static timing analysis and timing closure for chip physical design.
Details
- Found
- 21 d ago · posted 2026-09-04
- Location as listed
- Hyderabad
- Role
- Engineer (other)
- Source
- The company’s own careers site
Full description
Required skills:
Job Description:
Experience into STA and timing closure/signoff experience with PD domain skill-set/knowledge.
Candidate should be able to understand the timing constraints, analyze design details, analyze timing reports from prepcts to postcts stages, in-depth concepts of <14nm technode STA analysis, DCD knowledge.
Candidate is preferably expert in PT and Tempus tools.
Education Requirements
B. Tech / M. Tech (ECE)
Experience
5 to 12 Years
Location
Hyderabad
Shift
General
Work Week
Monday to Friday
Joining time
Immediate to 90 Days
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