The job in short
DFT (design-for-test) lead for semiconductor chips, owning test architecture, ATPG patterns and silicon bring-up.
Verilog
Details
- Found
- 22 d ago · posted 2026-09-11
- Location as listed
- Hyderabad
- Role
- Engineer (other)
- Source
- The company’s own careers site
Full description
Key Responsibilities:
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Lead DFT activity for the next generation products
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Driving the DFT architectures, methodologies and tool flows for complex multi-million gate designs with Analog/high bandwidth SerDes, DDR, PCIe designs
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Closely working with Physical implementation team to define timing constraints in test modes and helping to converge for successful tapeout
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Good understanding of ATE, knowledge of probe and final test bring up debug issues and drive the test engineering team for successful Silicon bring up and test program development
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Define the test plan by closely working with the design teams and drive the pattern development of functional/structural tests for final/wafer test program
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Closely working with the cross functional teams to bring up device qualification solution for HTOL
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Drive lab bench silicon debug to understand ATE bring up issues
Skills:
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Excellent communication skills, and strong team player with can do type of attitude
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Mentoring the team members
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Excellent debugging skills
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Process oriented to drive automation to help increase productivity and quality
Qualifications:
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12+ years of DFT experience including architecture specification, implementation, test pattern development, and simulation
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Proven track record of delivering DFT solution to complex designs
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Experience working with IJTAG methodologies, understanding device functionality
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Experience with hierarchical MBIST insertion, hierarchical scan insertion and scan compression methodologies
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Experience in ATPG pattern generation for different kinds of fault models, fault coverage analysis and converging to high coverage metrics
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Strong debug capabilities in simulating patterns with timing
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Experience in defining test mode constraints and analyzing the timing reports
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Experience with industry standard EDA tools for DFT, timing, and simulation
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Good knowledge of System Verilog
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Experience with chiplet based designs is a plus
Education:
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Bachelor of Engineering in Electronics and Electrical Engineering, Computer Engineering or similar fields (equivalent or higher)
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