DFT Engineer
Mirafra Technologies · mirafra.com
TempeSenior5–10 yrs
The job in short
DFT (design for test) engineering for ASICs: scan chains, ATPG and gate-level pattern verification.
Details
- Found
- 22 d ago · posted 2017-03-31
- Location as listed
- Tempe, AZ, US
- Role
- Engineer (other)
- Source
- The company’s own careers site
Full description
Company Description
About Mirafra :
Mirafra is software service base organization started in 2004.
We are 500+ employees in India and 250+ In US
Clear visibility to senior management which helps for constant professional growth
Job Description
Need knowledge of design for test (DFT) structures such as scan chains,
scan compression and verification concepts for test coverage (ATPG). Be
able to generate ATPG and analyze coverage results and how to extend or
optimize them. Need to know how to run gate simulation for to verify scan
patterns to demonstrate functionality.
Min Qualifications:
5 years experience in DFT in ASICs
Qualifications
10 years experience in DFT for large scale ASICs. Experience with Mentor
Graphics DFT tools.
Additional Information
All your information will be kept confidential according to EEO guidelines.
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