Key Responsibilities: • Design and implement sensor timing control logic and contribute to ISP system-level integration • Participate in chip-level architecture definition, including analog interfaces, control logic, image data processing pipelines, and power/performance/area (PPA) trade-offs • Integrate and validate ISP data paths based on PRD, design specifications, and overall SoC architecture • Collaborate closely with CIS project leads and sensor digital/analog engineers for system integration and validation • Work with physical design teams on floor planning, timing closure, and DFT implementation • Perform full-chip integration and verification • Support chip bring-up, validation, and silicon debugging • Collaborate with algorithm and application engineers on image tuning, optimization, and qualification • Support silicon validation, debugging, and image quality tuning through production readiness Minimum Qualifications • Bachelor’s degree in Electrical Engineering, Computer Engineering, or a closely related field, or equivalent practical experience • At least 2 years of hands-on experience designing RTL digital logic using Verilog/System Verilog, or equivalent industry experience • Proficiency with scripting languages such as Python or Perl to support design, verification, and automation workflows • Experience analyzing and optimizing area, power, and performance (PPA) trade-offs in digital designs Preferred Qualifications • Master’s degree or PhD in Electrical Engineering, Computer Engineering, or a related discipline • Strong background in image sensor and camera system design or integration • Experience with high-speed MIPI interfaces (e.g., CSI-2 / D-PHY / C-PHY) • Practical experience with Image Signal Processing (ISP) architectures and pipelines Annual base salary for this role in California, US is expected to be between $110,600 - $140,000. Actual pay will be determined on several factors such as relevant skills and experience, and the pay of employees in the similar role. EOE/Minorities/Females/Vet/Disability