Define and drive power integrity and signal integrity strategy for next-generation Cryo-CMOS quantum control systems. Own electrical integrity across silicon, package, PCB, interconnect, and system-level implementations. Architect and optimize power delivery networks spanning on-chip power grids, advanced packages, and board-level power distribution. Develop isolation strategies that enable large-scale digital switching circuitry to coexist with highly sensitive analog, RF, and qubit-control signals. Lead analysis and mitigation of power delivery, switching noise, electromagnetic coupling, crosstalk, and mixed-signal interference mechanisms. Drive silicon-package-board co-design activities in partnership with ASIC, package, board, system, and quantum hardware teams. Establish design methodologies, validation plans, and signoff criteria for power integrity and signal integrity closure. Correlate simulation results with laboratory measurements and provide technical leadership for critical architecture decisions across the organization. Other: Embody our culture and values. Doctorate in Physics, Engineering, or related field AND 1+ year(s) experience in industry or in a research and development environment, could include completion of a post doctoral research position OR Master's Degree in Physics, Engineering, or related field AND 4+ years experience in industry or in a research and development environment OR Bachelor's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment Ability to leverage AI tools to drive innovation and efficiency (e.g., performance modeling and analysis, research gathering, day to day task automation). Ability to work in an AI-first environment using modern AI tools to accelerate discovery through hardware development. Doctorate in Physics, Engineering, or related field AND 3+ years experience in industry or in a research and development environment, could include completion of a post doctoral research position OR Master's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment OR Bachelor's Degree in Physics, Engineering, or related field AND 8+ years experience in industry or in a research and development environment OR equivalent experience. Experience with power integrity and signal integrity for complex mixed-signal electronic systems, including power delivery network architecture, IR drop, voltage droop, simultaneous switching noise, ground bounce, return-current behavior, electromagnetic coupling, and transmission-line effects. Experience designing and analyzing power delivery networks across application-specific integrated circuits (ASICs), semiconductor packages, printed circuit boards (PCBs), and complete electronic systems, including silicon-package-board co-analysis and design optimization. Experience using industry-standard simulation tools such as Synopsys RaptorX, Ansys HFSS, SIwave, Cadence Clarity, PowerSI, Keysight ADS, Spectre, HSPICE, or equivalent environments. Experience correlating simulation results with laboratory characterization and measurement data. Experience designing large mixed-signal ASICs that integrate substantial digital content with sensitive analog, radio-frequency (RF), or precision measurement circuitry, including architectures requiring isolation between noise-generating and noise-sensitive systems. Experience with advanced packaging technologies, including 2.5D and 3D integration, silicon interposers, chiplet architectures, and advanced package substrates. Experience defining power integrity signoff methodologies and integrated silicon-package-board design flows. Familiarity with Cryo-CMOS circuits, cryogenic electronics, quantum computing hardware, superconducting systems, or advanced instrumentation. Experience leading cross-functional hardware programs and supporting the development of engineers across multiple disciplines.