Build the future nobody's dreamed of yet... are you ready to rethink the impossible? Architect and simulate DSP signal chains for automotive Ethernet PHYs: define features, performance targets, and algorithm specs for mixed-signal and digital teams Implement DSP algorithms (e.g., Filtering, Error Correction coding, echo cancellation, receiver equalization, and so on) in Verilog/System Verilog, ensuring adherence to design specifications Collaborate with the algorithm and systems teams to define hardware architecture Translate fixed-point MATLAB/C/C++ models into fixed-point, synthesizable HDL code RTL Design and implement timing recovery/synchronization blocks (CDR, tracking loops), including jitter tolerance and stability/latency tradeoffs Contribute to detection and coding / FEC integration: soft-information interfaces, performance/complexity tradeoffs, and linkKPIs Support silicon bring-up and lab debug: correlate model ↔ silicon, root-cause issues, and iterate on algorithms/specs Collaborate across architecture, design, verification, and applications to deliver implementable and testable solutions B.S. + 10 years (or M.S. + 7 years) in Electrical Engineering, Computer Engineering, or related field Strong fundamentals in digital communications and DSP, including probability/statistics Practical experience in high-speed wireline DSP, including some mix of: FFE/DFE, adaptation, CDR, MLSD/Viterbi concepts, FEC integration, fixed-point modeling Strong C++ and MATLAB skills for algorithm development, modeling, and analysis We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills.