The candidate for this position will be expected and able to complete the following responsibilities: Own and lead FPGA design environment efforts for rapid IP prototyping and design validation including root-cause analysis of complex system issues. Own development of custom IP RTL from microarchitecture through RTL implementation, verification, and post-silicon validation. Collaborate with architecture, SoC, firmware, verification, and physical design teams to deliver high-quality FPGA and IP solutions. Develop high-performance, power-efficient RTL designs and drive PPA optimization across the design lifecycle. Lead design signoff activities including CDC, RDC, LINT, and timing closure Mentor engineers and champion design excellence through reviews, automation, and continuous methodology improvements. Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. 4+ years experience in digital logic design in SystemVerilog/Verilog/VHDL 4+ years experience running synthesis/static check tools including RTL synthesis, lint, CDC, RDC, and/or LEC Expertise in digital design, microarchitecture specification development, and FPGA implementation. 5+ years of FPGA and RTL design experience Expertise in Verilog/System Verilog Expertise with FPGA designs (plan, build, troubleshooting, and debug) Ability to read and write Python code Experience developing and optimizing high-speed CMOS designs, including power, performance, and area tradeoff analysis Debugging, problem-solving, and cross-functional collaboration skills throughout the IP development lifecycle Written and verbal communication skills, with the ability to work independently and collaborate effectively across teams Experience with Xilinx FPGA boards and tooling Experience with ChipWhisperer or other similar FPGA power analysis tools Experience setting up infrastructure for test automation and results checking