If hired, you will be responsible for delivering TFM (tool, flow and methodology) of Physical Design tasks at block, sub-chip, and/or full-chip level. The roles include one or more of the following tasks - Place and Route (PnR), Static Timing Analysis (STA) and timing ECOs, Physical Verification (PV), Formal Equivalency Verification (FEV), Functional ECO, Global Clocking Construction, IR-Drop/EM (EMIR) and PD Infrastructure and IPs collaterals handling with details below: Lead the PnR convergence recipe development for designs at blocks/subsystem and subchip level Develop and implement methodologies and strategies to improve physical design efficiency and performance Develop and implement methodologies and strategies to sign off blocks, subsystem/Subchip in the areas of static timing analysis, physical verification, functional logics equivalence, low power verification and electromigration and IR drop Implementation of functional and timing ECO with least physical design impact Design and implement the global clocking scheme at SOC and sub chip levels Stay current with industry trends and emerging technologies to continuously improve physical design processes and methodologies Installation and quality check of internal and external IP collaterals for use by Physical Design execution team Conduct physical design reviews, identify and resolve design issues, and provide guidance to engineers. Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience. Other: This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. Bachelor's or Master's in Electrical or Computer Engineering or related field with 10+ years of experience Experience in tapeouts of complex ASICs in leading edge technology 10+ years of experience in blocks level place and route Expertise in one or more of physical design EDA tools such as Synopsys Fusion Compiler, PrimeClosure, Primetime, Formality, VCLP, Star-RC, Redhawk SC, and Cadence Innovus; Siemens Calibre. Understanding of semiconductor design principles, methodologies, and tools. Proven track record of successfully leading physical design projects and delivering high-quality semiconductor products Adequate scripting skillsets in TCL and Python Good understanding of foundry tech files and rule decks