Position Summary We are looking for a highly motivated Staff Digital Verification Engineer with 6-10 years of experience in ASIC/SoC verification. The ideal candidate will have strong expertise in System Verilog (SV) and UVM, along with hands-on experience in developing scalable verification environments, coverage-driven verification, and debugging complex RTL and gate-level issues. Exposure to Gate-Level Simulation (GLS) is required, while experience with fault injection simulations will be considered a strong advantage. #LI-DJ1 Key Responsibilities • Expected to take ownership and lead verification efforts across IP, subsystem, and SoC-level projects and work independently. • Independently Architect and develop reusable verification environments using System Verilog and UVM. • Create constrained-random, directed, and scenario-based test cases. • Develop scoreboards, monitors, protocol checkers, assertions (SVA), and coverage models. • Analyze and debug RTL and gate-level simulation failures for timing and functional signoff. • Analyze, debug, and enhance C/C++ golden reference models for functional verification. • Execute, and debug fault injection simulations to validate functional safety requirements and fault handling mechanisms. • Collaborate closely with design, DFT, physical design, and architecture teams to resolve issues and support sign-off activities. Work with AI-assisted engineering tools (e.g., GitHub Copilot, Microsoft Copilot, LLM-based code generation/debug tools, AI-driven verification productivity solutions) to enhance regression infrastructure and verification automation #LI-DJ1 • Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field. • 6-10 years of hands-on experience in Digital/ASIC/SoC Verification. • Strong expertise in: System Verilog (Mandatory) and UVM (Mandatory) • Familiarity with industry-standard simulators such as Xcelium and Questa. • Verification experience with some or all protocols such I2C, AHB/APB, MIPI #LI-DJ1