Job Details: Job Description: We are looking for a highly motivated Senior Physical Design Signoff Automation Engineer to develop and deploy signoff methodologies and automation solutions for advanced CPU and SoC designs. The candidate will work closely with Physical Design, Timing, Power, Reliability, and CAD teams to improve signoff quality, productivity, and turnaround time. The ideal candidate possesses deep expertise in Parasitic Extraction, Static Timing Analysis (STA), Electrical Rule Checking (ERC), and Power Integrity signoff, along with strong programming and automation skills. Key Responsibilities Develop and enhance automation solutions for Physical Design signoff flows, including: RC Extraction Static Timing Analysis (STA) Electrical Rule Checking (ERC) Power Integrity (IR Drop/EM) Signal Integrity (SI) Create scalable automation frameworks to reduce signoff turnaround time and improve engineering productivity. Develop scripts and tools to automate signoff checks, debugging, reporting, and data analysis. Analyze and resolve timing, extraction, ERC, and power signoff issues in collaboration with design teams. Drive methodology improvements to improve signoff convergence, quality, and correlation across implementation stages. Partner with EDA vendors and internal CAD teams to evaluate and deploy new signoff capabilities. Build dashboards and reporting infrastructure to monitor signoff health and project readiness. Qualifications: Minimum Qualifications M.Tech/M.S. in Electrical Engineering, VLSI, Computer Engineering, or related field. 8+ years of industry experience in Physical Design, Signoff, CAD, or Design Automation. Strong proficiency in: Python Tcl Shell scripting Preferred Qualifications Experience working on advanced process technologies (3nm, 2nm, Intel 18A/14A, or equivalent). Understanding of AOCV/POCV and variation-aware timing methodologies. Familiarity with power delivery networks, EM analysis, and reliability signoff. Experience in Machine-learning methods and Agentic AI systems to solve CAD problems Exposure to CPU core, high-performance compute, or large SoC designs. Experience with distributed computing environments and large-scale signoff infrastructure. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. * ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.