The candidate for this position will be expected and able to complete the following responsibilities: Own SOC implementation and integration strategies. Work with SOC Integration and IP Design Engineers to ensure RTL quality and timeliness. Continue to assess and refine implementation for area, power, and performance. Integrate various functional blocks into the SOC FPGA. Exercise the functionality of the block by writing basic tests and debug for various features at IP and SOC levels as deemed necessary. Lead the gate-level simulation team to complete goals on time with high quality. Perform design quality checks such as Lint, CDC, RDC, Low Power Intent. Work with the verification team to ensure Design quality. Challenge the status quo with a growth mindset. Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. 5+ years of technical experience/knowledge in SOC Integration. Demonstrated expertise in Computer Architecture, Digital Design, IP and SOC development. Highly proficient in Verilog/System Verilog. Experience with industry standard RTL tools and flows. Experience in high performance and low power design techniques. Experience in delivery of ASIC IPs, sub-systems and/or top-level SOC RTL for multiple projects. Experience in design flows and methodologies including Lint, CDC, RDC, synthesis, timing, and power analysis. Good understanding of IP development & SOC integration challenges at subsystem and full chip level. Experience with gate-level simulation. Experience with clock/reset design. Effective communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams. Proven track record of silicon delivery as a team leader. Experience in design for testability, debug, and manufacturing. Ability to write scripts using Python, Perl, Tcl, etc. Ability to leverage AI to improve efficiency and quality of deliverables. Experience in industry standard tools used for design abstraction, integration, and wiring. Experience in front end design flows and methodologies: SCM, RTL partitioning, third party IP integration, synthesis, CSR integration, memory map, and 1st order verification debug. Domain knowledge in one or more of these areas is a plus: PCIe, Fabric, Security, CPU, Coherence, high speed interfaces/protocols.