Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Role Overview Astera Labs is seeking a Quality Engineer to join our Product Quality Engineering team in San Jose, CA. This is an exciting opportunity for an early-career engineer to dive into the heart of AI infrastructure connectivity, working hands-on with cutting-edge semiconductor devices that power the world's most advanced data centers. In this role, you will be instrumental in driving root-cause analysis of failures across circuit, package, firmware, and protocol layers — directly impacting the reliability and quality of our PCIe and Ethernet connectivity solutions. You'll work with state-of-the-art lab instrumentation, build infrastructure to accelerate failure analysis, and collaborate across engineering disciplines to ensure Astera Labs continues to deliver best-in-class silicon to hyperscale customers. If you're passionate about high-speed SERDES, signal integrity, and solving complex hardware problems at the intersection of AI and connectivity, this is the role for you. Key Responsibilities • Failure Analysis & Root-Cause Infrastructure • Enable and develop infrastructure such as databases to optimize and reduce time to root-cause failures in circuit, package, firmware, or protocol-level iterations • Participate in the new product development process to enable improvements and capabilities for failure analysis • Document product quality engineering processes and methodologies to ensure repeatability and scalability • Lab Measurement & Debug • Perform measurements on high-speed SERDES, PCIe, and Ethernet devices to characterize and debug quality issues • Set up and use advanced lab instrumentation including BERT, high-bandwidth oscilloscopes, protocol analyzers, VNAs, TDR, and spectrum analyzers to support debug and root-cause activities • Cross-Functional Collaboration • Collaborate with design, validation, hardware, and system engineering teams to resolve quality issues and drive continuous improvement • Support cross-functional efforts to improve product reliability and manufacturing quality Basic Qualifications • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field • Understanding of high-speed serial interfaces (PCIe, Ethernet, SERDES) • Familiarity with lab instrumentation such as oscilloscopes, BERT, TDR, or spectrum analyzers • Strong analytical and problem-solving skills • Excellent documentation and communication skills Preferred Qualifications • Internship or project experience in semiconductor quality, product engineering, or hardware validation • Exposure to signal integrity concepts and high-speed measurement techniques • Experience with database tools or scripting languages (Python, SQL) for data analysis and infrastructure development • Familiarity with failure analysis methodologies in a semiconductor environment • Knowledge of PCIe or Ethernet protocol specifications The salary range for this position is $120,000 to $140,000 depending on experience and education level. This role may be eligible for discretionary bonus, incentives and benefits. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.