Key Responsibilities SoC DFT Architecture & Leadership  Own SoC-level DFT architecture and strategy for custom and platform-based SoCs.  Define and drive DFT implementation plans across multiple concurrent SoC programs.  Act as the technical authority and signoff owner for all DFT-related decisions and deliverables. Execution & Technical Ownership  Lead DFT RTL integration, scan insertion, and test architecture implementation.  Own and drive:  Scan, Compression, and ATPG strategy  MBIST, BISR, and redundancy implementation  JTAG / TAP, Boundary Scan, and debug infrastructure  Ensure DFT readiness across functional, scan, and low-power modes.  Collaborate with RTL, STA, and PD teams to ensure DFT-friendly design and implementation.  Drive ATPG pattern generation, simulation, and debug to ensure high test coverage and quality. Cross-Functional & Manufacturing Interface  Work closely with physical design teams to ensure scan and test logic closure with minimal PPA impact.  Interface with manufacturing, ATE, and OSAT teams on test requirements, vector delivery, and silicon bring-up.  Support post-silicon debug, yield ramp, and test optimization.  Represent Semifive in customer-facing technical discussions related to DFT strategy and signoff. Methodology & Team Development  Define and standardize DFT methodologies, flows, and checklists across Semifive programs.  Drive automation, scripting, and reuse to improve DFT efficiency and predictability.  Mentor and develop DFT engineers and leads, building deep technical and execution capability.  Review and approve DFT signoff reports and tapeout readiness criteria. Qualifications  B.E./B.Tech or M.E./M.Tech in Electrical / Electronics / VLSI Engineering.  12+ years of experience in DFT architecture and implementation for complex SoCs.  Proven track record of leading DFT implementation and signoff on multiple custom SoC tapeouts.  Strong expertise in:  Scan, Compression, and ATPG methodologies  MBIST, BISR, and memory repair schemes  JTAG / TAP and Boundary Scan  DFT RTL integration and pattern simulation  Hands-on experience with industry-standard DFT tools, such as:  Siemens Tessent  Synopsys DFTMAX / TestMAX  SpyGlass DFT (or equivalent)  Strong understanding of:  Low-power DFT challenges (UPF/CPF)  Scan and test-mode timing closure  Physical implementation constraints for DFT  Experience working with manufacturing, ATE, and post-silicon validation teams.  Excellent problem-solving, communication, and leadership skills.