The Compute Silicon & Manufacturing Engineering (CSME)'s Cloud Compute Development Organization (CCDO) is seeking a Senior SoC HW (Analog/Functional) Validation Engineer to join the post-silicon validation (functional and/or power/performance) team for our projects. We are responsible for delivering cutting-edge, custom SoC designs that can perform complex and high-performance functions in the most efficient manner. As a technical individual contributor in this high impact role on the team, you will: Own post-silicon validation of one of the following areas PLL, IO electrical/analog or functional IO interfaces. Define, guide, and contribute to the implementation of silicon debug tools and capabilities. Become an expert on the overall architecture, implementation of high-speed IO interfaces (PLL, PCI, CXL, etc.) and their interactions with other parts of the SoC, with the platform, and with software. Provide technical guidance, coaching, and mentorship to other engineers in your areas of expertise. Develop validation strategy, requirements, environments, tools, and methodologies including debug board and hardware/software requirements. Apply your knowledge of validation principles and techniques and your judgement to write test plans and implement them by developing test content, scripts, tools and other validation collateral. Execute content in post-silicon, triage and debug failures. Apply your growth mindset to learn and adapt in a complex and dynamic environment. Engage with partners to drive continuous improvement to the design, to validation plans/collateral, and methodology to prevent, reduce, and/or find bugs sooner, more easily, or more reliably. Delight your customers by providing high quality results on schedule. Provide technical leadership with respect and integrity. Apply your expertise towards pre-silicon verification plans, tests, and debug of your area. Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience. Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience. Applied understanding of Computer Architecture and CPU/SoC validation principles, including: Understanding of SoC subsystem, SoC system level, and platform level functionality and writing scripts/software with industry standard languages like Python or C/C++. Proficient communication, collaboration and teamwork skills and ability to lead, grow, and contribute to diverse and inclusive teams. Verification, logic development, analog validation, or validation tools experience as part of a CPU, SoC and/or IP development team Demonstrated leadership skills Validation of: Electrical: Serdes, IO, high speed interconnect, analog circuits Power and Performance Automation, Content Creation, or Tools/Scripts Development Ability to develop synthetic SoC validation Core, Coherency, Memory, and IO content to run on both bare metal and OS environments. Ability to develop sophisticated tools/scripts to support SoC validation debug activities such as maximum power, current transients, and register dumps. Understanding of board level schematics. Understanding system level software and firmware. Experience running silicon content on pre-silicon platforms such as emulation or FPGA. Demonstrated success in hardware/software debug efforts. Hands on expertise debugging silicon failures using on chip debug features (like trace or JTAG) as well as test equipment (like oscilloscopes, protocol analyzers, bit error rate testers, logic