The candidate for this position will be expected and able to complete the following responsibilities: Lead and Execute end-to-end PD flow from synthesis through place-and-route for multiple designs, ensuring completion of all signoff stages including timing, physical verification, EMIR, formal equivalence, and low-power verification. Responsible for clock construction and CTS. Drive methodology exploration activities to optimize SOC blocks for clock construction and related methodology. Coordinate with CAD, RTL/Design teams/DFT, Architecture team, Power & Performance team, Technology team & other internal/external partners as essential. Responsible for RTL to GDS implementation and ownership in Physical Design domain. Influence design tools, flows, and methodologies in construction, signoff, and optimization through a data-driven approach. Demonstrate leadership and technical expertise across various domains of Physical Design. Clear communications on project status & planning. Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 7+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 10+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experience OR equivalent experience. Track record in Physical Design domain implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification. 20+ years of experience in Physical design Production silicon tape-outs experience in advanced foundry process nodes. Experience in low power design methodology for SOC Understanding of SOC or subsystem design trade-offs across power, performance, and area (PPA). Familiarity with various clock construction strategies for high speed designs Demonstrate technical expertise in all aspects of Physical Design, from synthesis to place and route of partitions through all signoff including timing signoff, physical verification, EMIR signoff, Formal Equivalence, and Low Power Verification. Own complete PD execution of medium to large-size SOC block. Be fully hands-on in technical domain ownerships as individual contributor and collaborate cross-team as required. Partner closely with PD flow/CAD team and PD methodology team to flag & fix PD TFM issues Problem-solving and data analysis skills Ability to communicate effectively with cross-functional teams