The candidate for this position will be expected and able to complete the following responsibilities: Development and Integration of various functional block RTL related to SOC clock controllers Perform design quality checks such as Timing closure, Lint, CDC, Synthesis, Low Power Intent Utilize AI for gaining efficiency within process and development. Interface with verification team to ensure functional correctness. Interface with physical design, design-for-test, and other teams to deliver qualified physical partitions evaluating tradeoffs and delivering high quality design. Exercise the functionality of the block by writing basic tests and debug for various features at IP and SoC levels as deemed necessary. Automate tasks using scripting for efficiency Delight your customers by providing high quality functional blocks on schedule and with professional integrity Challenge the status quo with growth mindset. Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience OR equivalent experience. Citizenship & Citizenship Verification: This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their U.S. permanent residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. Minimum 2+ year logic design experience Knowledge of logic design flow including Low Power Analysis, UPF, RTL coding, Synthesis, timing constraints, timing closure. 2+ years of experience designing clock controller IP Proficient in Verilog/System Verilog coding constructs. Knowledge of front-end tools ( VCLP, Verilog simulators, Connectivity tools, low power static checkers, linting) Demonstrated experience and knowledge of clock crossings, and power/UPF in design Familiarity with Industry standard interface protocols (ARM) is a plus. Familiarity with Formal Equivalence Verification and Power Analysis is a plus. Good verbal and written communication skills.