Job Summary We are seeking a highly experienced Clocking/Constraints/STA Lead to join our Physical Design team. In this critical leadership role, you will not only be responsible for your own technical expertise but also for guiding and mentoring a team of engineers to achieve exceptional timing closure for our IC designs. Full Chip Static Timing Analysis (STA) Engineer verifies that an entire System-on-Chip (SoC) meets all speed and performance requirements across every operational condition without running full logical simulations Location: Bangalore/Hyderabad/Noida/Chennai Key Responsibilities Lead the development and implementation of comprehensive clocking strategies for high-performance ICs. · Define and manage timing constraints throughout the design flow, ensuring accurate and consistent timing analysis. · Stay up-to-date with the Perform advanced Static Timing Analysis (STA) using industry-standard tools, identifying potential timing violations and bottlenecks. · Develop and maintain robust clock tree synthesis (CTS) methodologies for optimal clock distribution and skew control. · Drive the creation and execution of a comprehensive clock domain crossing (CDC) verification plan. · Collaborate with design engineers, layout engineers, and other physical design teams to address timing closure challenges. · Mentor and coach junior engineers, fostering their growth and expertise in clocking, constraints, and STA. · latest advancements in clocking methodologies, timing analysis tools, and industry best practices. · Lead the evaluation and implementation of new tools and methodologies for improved timing closure efficiency. · Develop and maintain comprehensive documentation for clocking, constraints, and STA practices within the team. Skill Requirements Master's degree in Electrical Engineering, Computer Engineering, or a related field (preferred) or Bachelor's degree with extensive experience. · Minimum of 15+ years of experience in clocking, constraints, and STA for digital IC design. · Understanding of On-Chip Variation (OCV/POCV), clock tree architecture, parasitic extraction (SPEF), and gate-level netlists · Proven leadership experience in managing and motivating a team of engineers. · In-depth knowledge of digital design principles, timing analysis methodologies, and clock tree synthesis techniques. · Expert-level proficiency in industry-standard STA tools (e.g., Synopsys PrimeTime, Mentor Questa Timing Analyzer). · Strong understanding of clock domain crossing (CDC) verification concepts and methodologies. · Excellent communication, collaboration, and interpersonal skills. · Ability to think strategically, solve complex timing closure problems, and make sound technical decisions. · Proven ability to manage multiple projects and meet aggressive deadlines in a fast-paced environment. Other Requirements Skills: · Clocking · Timing constraint development (Full chip Must) · STA tools: Innovus, Synopsys PrimeTime, Mentor Questa Timing Analyze · Understanding of On-Chip Variation (OCV/POCV), clock tree architecture, parasitic extraction (SPEF), and gate-level netlists