The candidate for this position will be expected and able to complete the following responsibilities: Build a PCIe subsystem composed of multiple IP Collaborate with architecture and IP providers to ensure the subsystem meets SOC requirements. Grow your micro-architectural knowledge of your own blocks as well as other blocks in the SoC. Assess and then refine the implementation for area, power and performance. Perform design quality checks such as Synthesis, Lint, CDC, RDC, Low Power Intent, Logic Equivalence. Understand Dataflow and Clocking requirements and drive solutions for timing critical paths. Automate tasks using scripting for efficiency. Delight your customers who receive your deliverable by providing high-quality functional block on schedule and with professional integrity. Challenge the status quo with a growth mindset. Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience. Experience with high speed PCIe designs and protocols Experience with Industry standard interface protocols such as AXI, APB, etc. Experience with ARM Fabric IPs Experience with IPXACT Understanding of Computer Architecture fundamentals Ability to write scripts using Python, Tcl, Perl etc. Experience in EDA tools such as VCS, VCLP, Spyglass Lint, Questa CDC, Fusion Compiler, Design Compiler, Genus Proficiency with UPF (Low power intent). Proficiency in clock crossing techniques Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals. Applied understanding of low power design principles. Understanding design closure challenges with power and clock domain crossings. Experience writing timing constraints, exceptions, and clock constraints; good understanding in SDC commands and TCL constraints Organized and detail-oriented Good verbal and written communication skills.