Senior and manager-level jobs in S
As of 10 Nov 2026, 21 senior and manager-level jobs are open in S on company career pages; 1 were posted in the last 7 days.
Get new senior and manager-level jobs in S by email, the day they’re posted ↓
Who’s hiring this week
- Broadcom: 1 new
Open now
1–21 of 21, plus 1 newer ones with members for their first 5 days
| Role | Company | Location | Pay a year | Experience | Posted | Quick look |
|---|---|---|---|---|---|---|
| Backend Physical Design EngineerSenior | Broadcom | S On-site | – | 6+ yrs | ||
Backend Physical Design Engineer at Broadcom SoC backend physical design (floorplan, place and route, CTS, physical verification, STA closure, ECO)
SOC | ||||||
| PCIe Design EngineerSenior | Broadcom | S On-site | – | 14+ yrs | ||
PCIe Design Engineer at Broadcom PCIe subsystem RTL and SoC design, emulation and silicon debug
VLSISOCCustomer support | ||||||
| R&D Engineer IC DesignSenior | Broadcom | S On-site | – | 6+ yrs | ||
R&D Engineer IC Design at Broadcom SoC DFT engineering: DFT architecture, test insertion, ATPG pattern generation and post-silicon debug
SOC | ||||||
| R&D Engineer IC DesignSenior | Broadcom | S On-site | – | 8+ yrs | ||
R&D Engineer IC Design at Broadcom SoC DFT engineering (ATPG, MBIST, JTAG, pattern generation, post-silicon debug)
SOC | ||||||
| Staff DFT EngineerLead / Manager | Broadcom | S On-site | – | 8+ yrs | ||
Staff DFT Engineer at Broadcom SoC DFT engineer for ASIC designs (DFT architecture, ATPG, MBIST, pattern generation, post-silicon debug)
SOC | ||||||
| Staff DFT EngineerLead / Manager | Broadcom | S On-site | – | 6+ yrs | ||
Staff DFT Engineer at Broadcom SoC DFT engineer for ASIC designs (ATPG, MBIST, IJTAG, pattern generation, post-silicon debug)
SOCVerilog | ||||||
| R&D Engineer IC DesignSenior | Broadcom | S | – | 8+ yrs | ||
R&D Engineer IC Design at Broadcom SoC DFT engineering: DFT architecture, test insertion, ATPG pattern generation and post-silicon debug
SOC | ||||||
| DFT Senior EngineerSenior | Broadcom | S On-site | – | 5+ yrs | ||
DFT Senior Engineer at Broadcom SoC design-for-test engineering (DFT architecture, ATPG, MBIST, IJTAG, pattern generation, post-silicon debug)
SOC | ||||||
| DFT Senior EngineerSenior | Broadcom | S On-site | – | 5+ yrs | ||
DFT Senior Engineer at Broadcom SoC DFT engineer for ASIC designs (DFT architecture, test insertion, ATPG/MBIST pattern generation, coverage, post-silicon debug)
SOCVerilog | ||||||
| DFT EngineerSenior | Broadcom | S On-site | – | 8+ yrs | ||
DFT Engineer at Broadcom DFT engineer for MBIST, scan insertion, ATPG and ATE pattern development with yield analysis
| ||||||
| Identity and CyberSenior | Broadcom | S | – | 5+ yrs | ||
Identity and Cyber at Broadcom Identity and cyber security services
AuditCompliance | ||||||
| Staff Design EngineerLead / Manager | Broadcom | S | – | – | ||
Staff Design Engineer at Broadcom SOC physical design engineering (floorplanning, place and route, CTS, timing closure, physical verification)
SOC | ||||||
| Staff EngineerLead / Manager | Broadcom | S On-site | – | – | ||
Staff Engineer at Broadcom SOC physical design: floorplanning, placement, clock tree synthesis, routing, physical verification and timing closure
SOC | ||||||
| Senior EngineerSenior | Broadcom | S | – | – | ||
Senior Engineer at Broadcom Engineering
SOC | ||||||
| Senior EngineerSenior | Broadcom | S On-site | – | – | ||
Senior Engineer at Broadcom SOC physical design (floorplanning, place and route, CTS, physical verification, timing closure)
SOC | ||||||
| Staff Memory Circuit Design EngineerLead / Manager | Broadcom | S | – | – | ||
Staff Memory Circuit Design Engineer at Broadcom Memory circuit design engineering
| ||||||
| Senior Memory Circuit Design EngineerSenior | Broadcom | S | – | – | ||
Senior Memory Circuit Design Engineer at Broadcom Memory circuit design
| ||||||
| IO and MixedSenior | Broadcom | S | – | 5–15 yrs | ||
IO and Mixed at Broadcom IO and mixed-signal circuit design
| ||||||
| Staff Software EngineerLead / Manager | Broadcom | S | – | 8–12 yrs | ||
Staff Software Engineer at Broadcom Staff software engineering
PythonLinuxCustomer support | ||||||
| IC Design EngineerLead / Manager | Broadcom | S On-site | – | 12+ yrs | ||
IC Design Engineer at Broadcom DFT manager leading a design-for-test team for ASIC chips
SOC | ||||||
| Staff EngineerLead / Manager | Broadcom | S On-site | – | – | ||
Staff Engineer at Broadcom Multi-skilled RTL design and DFT verification for memory subsystems and BIST
EmbeddedVerilog | ||||||
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Questions
- How many senior and manager-level jobs are open in S right now?
- 23 listings are open on OpeningsFirst today, all from employers’ own career pages. 1 newer ones went to members by email, within hours of being posted.
- Which companies are hiring for senior and manager-level jobs in S this week?
- In the week to 10 November 2026, the most new senior and manager-level jobs in S came from Broadcom (1).
- Which site alerts me to new senior and manager-level jobs in S?
- OpeningsFirst emails new senior and manager-level jobs in S the day employers post them on their own career pages, checking 108,056 career sites. Many never reach LinkedIn or Naukri. Listings older than 5 days are free to browse here; 23 are open on this page now.
- How do I hear about new senior and manager-level jobs in S first?
- Members get new matching jobs by email at 8 am and 6 pm, within hours of being posted, so they apply among the first. It costs $9 a month.
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